1. Field of the Invention
The present invention relates to integrated circuits and more specifically to a method of manufacturing a bipolar transistor in a single polysilicon BiCMOS technology.
2. Description of the Related Art
BiCMOS integrated circuits combine bipolar junction transistors and complementary MOS (CMOS) transistors on a single chip (integrated circuit), furnishing a variety of functionality and exploiting the advantages of each type of process. Thus BiCMOS integrated circuits capitalize on the relatively fast speed and better analog performance of bipolar transistors while exploiting the low power dissipation and high packing densities of CMOS transistors.
An integrated circuit which is fabricated using one conventional BiCMOS technology is shown in FIG. 1. A BiCMOS integrated circuit 100 includes a silicon wafer substrate 102 having a bipolar region 128 and a MOS region 130 which are separated by regions of field oxide 104, 106 and 108. (Note that field oxide is made of silicon dioxide, which is commonly referred to as "oxide"). The BiCMOS integrated circuit 100 is fabricated by oxidizing a surface of the integrated circuit 100 to form a thin layer of gate oxide 118 on the surface of the silicon wafer substrate 102 and the field oxide regions 104, 106 and 108. A thin layer of polysilicon 120 is deposited over the gate oxide layer 118, extending throughout the integrated circuit 100 surface. A layer of photoresist is applied to the surface of the polysilicon layer 120, masked and removed so that the layers of gate oxide 118 and thin polysilicon 120 remain only at the positions of a bipolar transistor 160 and a CMOS transistor 162. Thus, a bipolar gate oxide layer 170 and a bipolar thin polysilicon layer 172 remain at the position of the bipolar transistor 160 and a CMOS gate oxide layer 180 and a CMOS thin polysilicon layer 182 remain at the position of the CMOS transistor 162. A thick layer of polysilicon 124 is deposited over the BiCMOS integrated circuit 100 surface. A layer of photoresist is applied to the surface of the thick polysilicon layer 124, masked and etched so that the layer of thick polysilicon 124 is positioned only over the bipolar gate oxide layer 170 and bipolar thin polysilicon layer 172 to form an emitter 110 at the position of the bipolar transistor 160 and positioned over CMOS gate oxide layer 180 and CMOS thin polysilicon layer 182 to form a gate 190 at the position of the CMOS transistor 162.
One disadvantage of a BiCMOS circuit 100 that utilizes this approach is that the base resistance (R.sub.b) of the bipolar transistor is increased due to bipolar gate oxide layer 170 and bipolar thin polysilicon layer 172. These layers prevent adequate doping of the substrate beneath the emitter using ion implantation or lightly doped drain (LDD) implants, resulting in a lightly doped area under a non-active emitter at the emitter edges. Bipolar gate oxide layer 170 and bipolar thin polysilicon layer 172 are used in the fabrication process to set an end point to the etching process that is used to form the emitter 11O and the gate 190. Without such an end point, the polysilicon etching process would continue to etch into the substrate 102 which is also made of silicon.
To avoid this increase in R.sub.b, an alternative conventional BiCMOS fabrication process has been employed in which the etching process for forming a bipolar emitter and a CMOS gate does not attempt to set an end point at the polysilicon/silicon boundary but rather allows trenching into the silicon substrate. An integrated circuit which is fabricated using this alternative conventional BiCMOS technology is shown in FIG. 2. This BiCMOS integrated circuit 200 also includes a silicon wafer substrate 202 having a bipolar region 228 and a MOS region 230 and separating regions of field oxide 204, 206 and 208. The BiCMOS integrated circuit 202 is also fabricated by oxidizing the integrated circuit 200 to form a thin layer of gate oxide 218 and depositing a thin layer of polysilicon 220. However, in this process a layer of photoresist is applied to the surface of the polysilicon layer 220, masked and removed so that the layers of gate oxide 218 and thin polysilicon layer 220 remain only at the positions of a CMOS transistor 262. Thus, only a CMOS gate oxide layer 280 and a CMOS thin polysilicon layer 282 remain at the position of the CMOS transistor 262. A thick layer of polysilicon 224 is deposited over the BiCMOS integrated circuit 200 surface and a layer of photoresist is applied to the surface of the thick polysilicon layer 224, masked and over-etched so that the layer of thick polysilicon 224 is positioned only over the substrate 202 to form an emitter 210 at the position of the bipolar transistor 260 and positioned over CMOS gate oxide layer 280 and CMOS thin polysilicon layer 282 to form a gate 290 at the position of the CMOS transistor 262. The over-etching process for bipolar emitter 210 forms trenches 250 into substrate 202.
The BiCMOS process using trenching thus greatly reduces the increase in base resistance R.sub.b of the bipolar transistor. However, the trenching into the silicon substrate causes various problems which affect the ability to manufacture bipolar transistors that operate in a consistent manner. The concentration of the etching agent and the physical conditions of the etching process must be tightly controlled so that the fabricated BiCMOS circuits have similar operating characteristics. Tight control of the manufacturing process is difficult to achieve, as is evidenced by trench depths across a single wafer that commonly vary by 20-30%. The trenching process must be precisely controlled, not only to avoid trenches that are too deep, but also to avoid a degree of over-etching that is insufficient.
Excessive over-etching is disadvantageous because characteristics of the emitter/base junction of a bipolar transistor, including a propensity for short-circuiting, are influenced by the relative angle of the lateral sides of the emitter with respect to the surface of the substrate, called the vertical profile of the emitter. It is advantageous to have a vertical profile in which the sides of the emitter are perpendicular to the substrate surface. The vertical profile of the emitter, i.e., the tapering of the foot of the polysilicon emitter, is controlled when the polysilicon etch endpoints on an oxide layer. As a trench penetrates deeper into the substrate, a vertical profile cannot be attained.
Furthermore, if the over-etch is excessive and the trench is sufficiently deep that the emitter-base junction connection is impaired or essentially severed, the base resistance R.sub.b is raised to a level that disrupts or terminates operability of the transistor.
If the over-etch is insufficient, subsequent deposition of polysilicon can create bridging between the emitter and base via what are called polysilicon stringers. This occurs due to the isotropic/anisotropic nature of the etching process and leads to short-circuiting of the emitter-base junction. The over-etch must be sufficient to prevent polysilicon stringers but not so excessive that R.sub.b is increased.
An additional problem arising in BiCMOS technology is that over-etching should be precisely controlled for both bipolar and CMOS transistors but that the amount of over-etching for each transistor type is not always the same. For example, a desired amount of over-etching for a MOS transistor having a gate overlying a thin layer of polysilicon and a layer of gate oxide is different from an appropriate amount of over-etching for a bipolar transistor having a polysilicon emitter adjacent to silicon substrate.